The present invention relates to circuits and more particularly to a circuit arrangement for use in a register for the built-in self test of integrated circuits.
A known circuit arrangement is shown in FIG. 1 of the accompanying drawings and comprises two AND gates 3,8 coupled to a flip-flop 2 by means of an Exclusive OR gate 4. When the circuit arrangement is in use each of the inputs of the AND gate 8 respectively receives data input signals DI and control signals from a control line A, whilst each input of the AND gate 3 respectively receives serial input signals SI and control signals from a control line B. If a number of the circuit arrangements of FIG. 1 are arranged in series they form the basis of a known Built-In Logic Block Observation (BILBO) register. Such a register is illustrated in FIG. 2a of the drawings and the equivalent circuit for each of the modes of operation are shown in FIGS. 2(b-e).
FIG. 2a shows a five bit BILBO register of known type comprising five D-type flip-flops 2 coupled in series, the input of the first D-type flip-flop 2 in the series being connected to the output of an Exclusive-OR gate 14 and the inputs of each of the other four D-type flip-flops 2 in the series being connected similarly to the output of a respective Exclusive-OR gate 4. One of the inputs of the Exclusive-OR gate 14 is connected to the output of an AND gate 12 and similarly one of the inputs of each of the Exclusive-OR gates 4 is connected to the output of a respective AND gate 3. The other input of each of the Exclusive-OR gates 14, 4 is connected to the output of a respective AND gate 8. The inputs of each of the AND gates 8 are connected respectively to a common line A and to a respective output of a combinatorial logic network (not shown). The inputs of each of the AND gates 3 are connected respectively to a common line B and the output of one of the flip-flops 2, each of the inputs of the AND gate 12 being connected respectively to the common line B and the output of a multiplexer MUX.
The outputs of the second and fifth D-type flip-flops 2 in the series are connected to the inputs of an Exclusive-OR gate 10 the output of which is coupled to the input of the first D-type flip-flop 2 via the multiplexer MUX, the AND gate 12 and the Exclusive-OR gate 14. In practice only certain combinations of outputs from the D-type flip-flops 2 can be tapped for these feedback connections if it is desired to provide a maximal length test pattern when the BILBO register is in its test pattern generator mode. These combinations of outputs are known in the electronic field and are dependent on the number of D-type flip-flips 2 in the BILBO register.
The values of the signals on control lines A and B control the different functions that the BILBO register can perform. SCAN-IN is the scan-in input to the BILBO register, SCAN-OUT is the scan-out output for the BILBO register and the five output values for the D-type flip-flops 2 appear at the five output lines C.sub.1, C.sub.2, C.sub.3, C.sub.4 and C.sub.5. The output line C.sub.5 also serves as the SCAN OUT.
There are five modes of operation for the BILBO register. The first is illustrated in FIG. 2b with the signals on the lines A and B equal to 1 and 0 respectively. This is a mode of operation in which the input values from the combinatorial logic network are loaded into the D-type flip-flops 2, and the outputs on the five lines C.sub.1, C.sub.2, C.sub.3, C.sub.4 and C.sub.5 are available for system operation. The BILBO register behaves therefore with a normal register function.
In the second mode of operation, illustrated in FIG. 2c, the values of the control lines A and B are 0 and 1 respectively and a control line C to the multiplexer MUX is set so as to connect the scan-in input to the input of the AND gate 12, through the multiplexer MUX. In this mode the BILBO register behaves as a linear shift register, that is in a scan path mode.
In FIG. 2d the values on the control lines A and B are 0 and 1 respectively and the control line C to the multiplexer MUX is set so as to connect the feedback line to the input of the AND gate 12. In this third mode, the BILBO register behaves as a pseudo-random number generator useful in providing test patterns for a combinatorial logic network coupled to its output lines C.sub.1, C.sub.2, C.sub.3, C.sub.4 and C.sub.5, it is therefore referred to as being in its test pattern generator mode.
In FIG. 2e the values on the control lines A and B are both 1 and the control line C to the multiplexer MUX is set to connect the feedback line to the input of the AND gate 12. In this fourth mode the BILBO register behaves as a linear feedback shift register with multiple linear inputs. If the predetermined input signals are fed to a correctly functioning combinatorial logic network and the outputs of the combinatorial logic networks are connected to the inputs of the BILBO in this mode then after a large number of shift clocks there will be a characteristic signature left in the BILBO register for that correctly functioning logic network. Hence the mode is referred to as a signature analyser mode. The signature of the combinatorial logic network can be off-loaded from the BILBO register to the SCAN-OUT output by changing to the Scan Path Mode of FIG. 2c, that is by changing the values of the control lines A and B to 0 and 1 respectively.
In the fifth mode of operation the values on the control lines A and B are both set at 0 in which mode the BILBO register of FIG. 2a executes a synchronous reset.
We have found that the above described BILBO circuit arrangement and the BILBO register described above with reference to FIGS. 1 and 2, because of the restricted number of functional modes of operation, has limitations when incorporated into a built-in self testing integrated circuit, particularly a very large integrated circuit.
The present invention has as one of its objects the provision of a circuit arrangement having a larger number of functional modes of operation than the BILBO described above such as to facilitate the design and self testing facility of built-in self test integrated circuits.